I. Field of the Disclosure
The technology of the disclosure relates generally to bus systems shared among multiple master devices.
II. Background
Modern computer processors make use of a variety of bus standards to provide connectivity among master devices and between master devices and slave devices. One type of bus standard provides a shared bus protocol, under which a bus resource may serve more than one master device. Each master device may use its own reference clock signal to synchronize internal communications and operations, with each reference clock signal potentially being asynchronous in relation to others. As a consequence of using asynchronous reference clock signals, synchronizing operations involving more than one master device without a common clock signal external to the master devices may pose challenges.
Bus arbitration for determining which master device may use a shared bus for data transfer at a given time is one example in which synchronizing operations among multiple master devices may be problematic. Some bus protocols provide that, at any given time, one master device is known to be the bus master. The bus master drives the bus data and clock lines until mastership is handed over to the next bus master. Under these protocols, arbitration to determine the bus master for a next data transfer is carried out using a bus clock signal provided by the current bus master.
However, some bus protocols do not provide for an agreed upon clock owner during arbitration. Such protocols may provide “clockless” arbitration based on the reference clock signals of the master devices participating in arbitration. With clockless arbitration, the master devices implement a time-based protocol for generating a clock signal for arbitration, to be followed after a defined start event occurs. However, clockless arbitration typically requires restrictions on the reference clock signals to account for clock drifts and differences in clock phase and frequency. As a result, clockless arbitration may be difficult to implement and manage, and reference clock restrictions for clockless arbitration may hamper the design flexibility of chip designers.